This application incorporates by reference of Taiwan application Serial No. 090100317, filed on Jan. 5, 2001.
1. Field of the Invention
The invention relates in general to a method for measuring a full frame size from a display signal and an apparatus therefor, and more particularly to a method for measuring a fill frame size from a display signal by a data enable signal and an apparatus therefor.
2. Description of the Related Art
For maintaining the display quality, a display monitor, such as a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, is required to adjust the size and position of the full frame indicated by a display signal applied to the display monitor. In order to display frames indicated by the display signal in a proper position on the screen of the display monitor, the display monitor requires determining the display parameters such as a full frame size. For illustrating the problem behind a conventional approach, the following description will explain the circuitry of the display monitor, the display signal, and the determination of the full frame size and position.
The circuitry for a display monitor is illustrated in FIG. 1. The display monitor includes a differential signal receiving/decoding device 110 and a ratio processing device. A display signal applied to a display monitor is generally a low voltage differential (LVD) encoded signal. The LVD encoded signal is indicative of signals including three primary color signals, a horizontal synchronous signal Hs, a vertical synchronous signal Vs, a data enable signal DE, and a pixel clock CK. In FIG. 1, the LVD encoded signal 102 includes signals denoted by Rx0xe2x88x92, Rx0+, Rx1xe2x88x92, Rx1+, Rx2xe2x88x92, Rx2+, RxCxe2x88x92, and RxC+. Since the display monitor can only display digital signals, before processing these signals, the display monitor employs a differential signal receiving/decoding device 110 to convert and decode these signals into a digital display signal 104. On receiving the LVD encoded signal 102, the differential signal receiving/decoding device 110 converts and decodes the LVD encoded signal 102 into the digital display signal 104 (i.e., three primary color signals including red (RD), green (GD) and blue (BD) signals), the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, the pixel clock signal CK, and so on. When the digital display signal 104 is applied to a ratio processing device 130, an optimal output video signal can be obtained by phase adjustment or interpolation provided by the ratio processing device 130. Since the phase adjustment or interpolation is not the key to the measurement of the full frame size, they will not be described for the sake of brevity. The operation of the display monitor with the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, the pixel clock signal CK will be described in the following.
The horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock signal CK have units of frequency. The pixel clock signal CK indicates number of pixels to be displayed per second and determines intervals between a pixel to display color and the next one to display color. Upon receiving data of a frame, the display monitor displays colors of pixels of the frame line by line. First, the first pixel of the first line displays color. Second, the second pixel of the first line displays color. The process proceeds in the similar manner until the last pixel of the first line display colors. Next, the next line, such as the second line, display colors in the same manner from the first pixel to the last pixel. Likewise, the process proceeds until the last pixel of the last line displays color. Due to persistence of vision provided by human vision system, all of the pixels on the screen form the required frame. On receiving another frame, the display monitor displays the frame according to the same manner. It should be noted that, after the last pixel of each of the lines displays color, the horizontal synchronous signal Hs causes the scanning of pixels for displaying color to proceed from the first pixel of the next line. Thus, the horizontal synchronous signal Hs determines the number of rows of pixels to be display color per second. In addition, after the pixel of the last column and last row displays color, the vertical synchronous signal causes the scanning of pixels for displaying color to proceed from the pixel at the first column and first row. Thus, the vertical synchronous signal determines the number of frames to be displayed per second. Since human vision system provides persistence of vision, the frames displayed at a rate faster than a threshold value will become continuous movement of objects, i.e., a movie picture. The rate that the display monitor refreshes different frames on the screen is called a refresh rate, i.e., the frequency of the vertical synchronous signal Vs. The refresh rate for generally computer display systems is 60 Hz or above; i.e., the display monitor displays at least 60 frames per second. In the following, the timing relationship of the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock signal CK will be explained.
FIG. 2 illustrates the timing relationship of the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the data enable signal DE. Take the resolution of 1024xc3x97768 pixels as an example. For this resolution, the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the pixel clock signal CK can be 48.36 kHz, 60 Hz, and 65 MHz respectively. During displaying frames, 60 frames are displayed for every second and the Vs signal changes its state only after 768 cycles of the Hs signal because there are 768 rows per frame. In addition, the data enable signal DE determines the period of the display of each row. For each row, 1024 pixels are required to be displayed. Thus, when the enable signal DE is asserted, the display monitor displays colors of 1024 pixels. Having a fixed frequency, the pixel clock signal CK correspondingly oscillates for 1024 cycles during the assertion of the data enable signal DE, as shown in FIG. 2B. The color information of the 1024 pixels is then obtained by sampling the digital display signal through the pixel clock signal CK and the sampled color information is applied to the 1024 pixels during the assertion of the data enable signal DE. Thus, the data enable signal DE can be used to determine the width of the full frame size.
FIG. 3 further illustrates how a display area relates to the above-mentioned signals. A display area 300 shown in FIG. 3 indicates an array of 1024xc3x97768 pixels. Since the color of each pixel in the display area 300 is displayed by sampling the digital display signal through the pixel clock signal CK, all of the pixels of each row correspond to 1024 pulses of the pulse train of the pixel clock signal CK. As shown in FIG. 3, the length of each row on the display area 300 is determined by the data enable signal DE when the data enable signal DE is asserted. Although the horizontal synchronous signal Hs determines the display of each row on the display area 300, the length of the each row is not determined by the Hs signal. Besides, after the beginning and before the ending of every time interval during which the Hs signal is asserted, there are time intervals during which the Hs signal does not correspond to the display area 300 (i.e., time intervals during which the Hs signal correspond to areas outside the display area 300 and without pixels to be displayed), wherein the time intervals are commonly referred to as a back porch and a front porch respectively. For example, on the left side of the display area 300, a rectangle with dotted borders corresponds to a back porch BPH of the Hs signal. On the right side of the display area 300, a rectangle with dotted borders corresponds to a front porch FPH of the Hs signal. In addition, the vertical synchronous signal Vs similarly has its front and back porches. On the upper side of the display area 300, a region with dotted borders corresponds to an interval during which the Vs signal does not correspond to the display area 300, and is referred to as a back porch BPV of the Vs signal. On the lower side of the display area 300, a region with dotted borders corresponds to another interval for the Vs signal, i.e., a front porch BPV of the Vs signal. It is more important that the name xe2x80x9cporchxe2x80x9d is accepted through common practice so as to refer to the time intervals for the synchronous (Hs or Vs) signal during which the synchronous signal (Hs or Vs) corresponds to areas outside the display area and without pixels to be displayed.
In order to display frames indicated by the display signal in a proper position on the screen, a conventional display monitor generally adjust the full frame size and position of frames indicated by the display signal applied to the display monitor through a comparison between the display signal and a number of display signal settings provided in the display monitor. To be specific, the frequencies and polarities of the Hs and Vs signals are compared with the display signal settings provided on the display monitor. If the frequency and polarity of the horizontal synchronous signal Hs of the display signal is determined to be identical to one of the display signal settings provided in the display monitor, the display monitor uses the frame adjustment data for the determined display signal setting to adjust the frames indicated by the display signal, thereby displaying the frames in a proper position. However, since various video adapters are available on the market, even if the frequency and polarity of a display signal from a video adapter is determined to be identical to one of the display signal settings provided in the display monitor, timings for the front and back porches for the display signal may be different from that for the determined display signal setting. In this case, if the frame adjustment data for the determined display signal setting are used for frame adjustment, improper adjustment will occur and the frames cannot be displayed on the proper position on the screen, thus degrading the quality of display. For example, the frame may be displayed on the area with deviation or the total number of pixels is incorrect.
For resolving the above problem, control chips for accurately determining the timings of front and back porches for a display signal are developed. However, these control chips employ a method to determine the front and back porches by the first and last pixels of a frame indicated by the display signal, where the first and last pixels of the frame display color other than the black. If non-full-size frames or frames displaying black are applied to the control chip, the determination of the timings of the front and back porches may produce unexpected results, wherein the frames displaying black have no red, green, and blue, such as the black screen in a command mode.
It is therefore an object of the invention to provide a method for measuring a full frame size from a digital display signal and an apparatus therefor. Regardless of the patterns of the display frames indicated by the digital display signal, the full frame size can be determined accurately, even if the display frame to be display is black or non-full frame.
The invention achieves the above-identified object by providing an apparatus for measuring a full frame size from a digital display signal by a data enable signal, wherein the digital display signal includes a primary color signal with a number of display bits. The apparatus includes a timing control device and a multiplexing device. The timing control device has multiple input terminals and a control signal output terminal. Each of the input terminals is capable of being coupled to a display bit of the primary color signal. The timing control device outputs a control signal through the control signal output terminal. In addition, the control signal is used to indicate whether to make display adjustment. The multiplexing device is coupled to the timing control device, the data enable signal, and an nth bit of the primary color signal. According to the control signal, the multiplexing device selectively applies either the data enable signal or the nth bit of the primary color signal to an nth input terminal of the input terminals of the timing control device, wherein n is not greater than m and m and n are integer greater than zero.
When the actual frames of the digital display signal are to be displayed, the nth bit of the primary color display bit is selected and applied to the timing control device through the multiplexing device. When the timing control device is to perform display adjustment, the timing control device outputs the data enable signal to the multiplexing device and the multiplexing device applies the data enable signal to the timing control device. According to the data enable signal, the timing control device can determine the display parameters, such as the front and back porches, so as to obtain the full frame size and position. After the display adjustment, the timing control device changes the logic state of the data enable signal so that the input terminals of the timing control device receive the primary color signal with its original display bit arrangement, thus allowing the frames indicated by the display signal to be displayed according to the display adjustment.
According to the invention, a method for measuring a full frame size from a display signal by a data enable signal is provided, wherein the display signal includes a primary color signal with m display bits. The method includes the following steps. First, the data enable signal is provided. A substituting display signal is then provided by substituting the data enable signal for an nth bit of the primary color signal. Finally, the full frame size is measured according to the data enable signal, wherein n is not greater than m and m and n are integer greater than zero.
As mentioned above, the data enable signal is substituted for one display bit of the primary color signal. According to the invention, the data enable signal can be substituted for another single display bit or multiple display bits in different manner so as to measure the display parameters. For example, the data enable signal can be substituted for another display bit of the primary color signal, or a number of the display bits of the primary color signal, or a single or multiple display bits of another primary color signal that is applied to the timing control device.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to accompanying drawings.